The code is:
if load(t–1) then out(t) = in(t–1)
else out(t) = out(t–1)
and according to fig (I can't copy the fig here but look in the book yourself), the in is at '0' selection of mux and out is at '1'. so if I am not wrong, I think there is slight misinterpretation of the mux code here:
this should be the other way round. i.e. the in should be at '1' selection of mux and out at '0'. in which case the code given above (as well as the general convention of loading a register on sel=1) will be right.
but if I am wrong, please explain!
Multiplexors (and demultiplexors) in schematic diagrams are usually drawn with one or more of the inputs labeled so that there is no ambiguity. When they are not labeled, then you must determine which inputs are where from context, as you did.
Also, the select input can be on top or bottom, and often a trapezoid is used as the outline instead of a triangle.