Why is this setup for my Mux16 not working? It says sub bus of internal node may not be used and refers to the x[0], but I really don't understand what that even means and I've been searching up and down the forums and even threads that talk about that same problem just make no sense to me and I've ready over appendix A many times. Also, is there any way to connect all my notsels and sels to an And16, when I tried this earlier it told me the bus widths did not line up which does make sense, but how would expand the width?
Here is my nonworking Mux16: CHIP Mux16 { IN a[16], b[16], sel; OUT out[16]; PARTS: Not(in=sel, out=notsel); And(a=notsel, b=a[0], out=x[0]); And(a=notsel, b=a[1], out=x[1]); And(a=notsel, b=a[2], out=x[2]); And(a=notsel, b=a[3], out=x[3]); And(a=notsel, b=a[4], out=x[4]); And(a=notsel, b=a[5], out=x[5]); And(a=notsel, b=a[6], out=x[6]); And(a=notsel, b=a[7], out=x[7]); And(a=notsel, b=a[8], out=x[8]); And(a=notsel, b=a[9], out=x[9]); And(a=notsel, b=a[10], out=x[10]); And(a=notsel, b=a[11], out=x[11]); And(a=notsel, b=a[12], out=x[12]); And(a=notsel, b=a[13], out=x[13]); And(a=notsel, b=a[14], out=x[14]); And(a=notsel, b=a[15], out=x[15]); And(a=sel, b=b[0], out=y[0]); And(a=sel, b=b[1], out=y[1]); And(a=sel, b=b[2], out=y[2]); And(a=sel, b=b[3], out=y[3]); And(a=sel, b=b[4], out=y[4]); And(a=sel, b=b[5], out=y[5]); And(a=sel, b=b[6], out=y[6]); And(a=sel, b=b[7], out=y[7]); And(a=sel, b=b[8], out=y[8]); And(a=sel, b=b[9], out=y[9]); And(a=sel, b=b[10], out=y[10]); And(a=sel, b=b[11], out=y[11]); And(a=sel, b=b[12], out=y[12]); And(a=sel, b=b[13], out=y[13]); And(a=sel, b=b[14], out=y[14]); And(a=sel, b=b[15], out=y[15]); Or16(a=x[0..15], b=y[0..15], out=out[16]); } 
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The "sub bus of an internal node may not be used" error is an annoying limitation of HDL. All buses must be created at their full width when connected to a part output. You can connect multiple wires and buses to a part output so you can create multiple narrower buses from a wide output, but you cannot connect multiple part outputs to make a bus. Your code would need to read something like Assuming that you have a working Mux.hdl, why are you replicating its lowlevel implementation 16 times? The layersofabstraction thinking that TECS encourages would have you think about how you can use what you've already built to build your Mux16.And(a=notsel, b=a[0], out=x0); And(a=notsel, b=a[1], out=x1); And(a=notsel, b=a[2], out=x2); ... Or16(a[0]=x0, a[1]=x1, a[2]=x2,... The easiest way to make a single signal a buswide signal is but that doesn't help much in making a Mux16.Mux16(sel=signal, a=false, b=true, out=signal16); Mark 
It seems like that there is not a way to code an array of muxes in the PARTS: section of the MUX16 and that I will have to add 16 lines of code there (16 MUX calls), is this correct? With MUX16 it seems like a copynpaste problem, not an issue, but what if you had a MUX64. Do people typically script it to modify the hdl code?
It seems my solution will be something like this. CHIP Mux16 { IN a[16], b[16], sel; OUT out[16]; PARTS: Mux(fill in details); // Mux 1 Mux(fill in details); // Mux 2 Mux(fill in details); // Mux 3 Mux(fill in details); // Mux 4 Mux(fill in details); // Mux 5 Mux(fill in details); // Mux 6 Mux(fill in details); // Mux 7 ... Mux(fill in details); // Mux 16 } Thanks for the insights and help 
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