Well I understand that to implement 4way mux we need to compare first two outputs with sel0 and remaining two outputs with sel0 parameter and the result with sel1 . But my doubt here is two select pins must be taken into consideration at the same time before selecting the final output.but why we are using sel0 for first two comparison and sel1 for the other.??

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Hardware buses are numbered from right to left, starting with 0. Here's the truth table for Mux4Way16 showing the index numbers for the sel bus. sel  out [1] [0]   0 0  a 0 1  b 1 0  c 1 1  dThe reason for this numbering order is so that when a bus is carring a binary number, bus[n] is the 2^n weighted bit of the number. This will make more sense when you get to chapter 2. Mark 
Well I was wondering what will happen if we evaluate first two inputs a and b with sel 0 and c and d with sel 1 and the result again with sel 0. What could be wrong in this. On 3 Jan 2018 2:37 am, "cadet1620 [via Nand2Tetris Questions and Answers Forum]" <[hidden email]> wrote: Hardware buses are numbered from right to left, starting with 0. Here's the truth table for Mux4Way16 showing the index numbers for the sel bus. 
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From your original post:
From latest post: The second circuit may have the same parts, but they are not connected the same so it doesn't work. This is like asking, "I can make And using Not(Nand(a,b)) so why can't I make And using Nand(a,Not(b))?" You can use a truth table, Boolean Algebra, or a program like Logisim to figure out what weird function your second circuit is computing. Mark 
Yes I understood that but some basics am a bit confused.. like how to get into the idea of using two mux and also which selection bit to use. Is it while using 2 way mux we have to consider oly Sel0 and while combining oly we have to use Sel1 On 3 Jan 2018 8:55 am, "cadet1620 [via Nand2Tetris Questions and Answers Forum]" <[hidden email]> wrote: From your original post:From latest post: 
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