# 4 way 16 bit mux

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## 4 way 16 bit mux

 Well I understand that to implement 4way mux we need to compare first two outputs with sel0 and remaining two outputs with sel0 parameter and the result with sel1 . But my doubt here is two select pins must be taken into consideration at the same time before selecting the final output.but why we are using sel0 for first two comparison and sel1 for the other.??
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## Re: 4 way 16 bit mux

 Administrator freak wrote Why we are using sel0 for first two comparison and sel1 for the other.?? Hardware buses are numbered from right to left, starting with 0.  Here's the truth table for Mux4Way16 showing the index numbers for the sel bus. ``` sel | out [1] [0] | --------|----- 0 0 | a 0 1 | b 1 0 | c 1 1 | d ```The reason for this numbering order is so that when a bus is carring a binary number, bus[n] is the 2^n weighted bit of the number. This will make more sense when you get to chapter 2. --Mark
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## Re: 4 way 16 bit mux

 Well I was wondering what will happen if we evaluate first two inputs a and b with sel 0 and c and d with sel 1 and the result again with sel 0.What could be wrong in this.On 3 Jan 2018 2:37 am, "cadet1620 [via Nand2Tetris Questions and Answers Forum]" <[hidden email]> wrote: freak wrote Why we are using sel0 for first two comparison and sel1 for the other.?? Hardware buses are numbered from right to left, starting with 0.  Here's the truth table for Mux4Way16 showing the index numbers for the sel bus. ``` sel | out [1] [0] | --------|----- 0 0 | a 0 1 | b 1 0 | c 1 1 | d ```The reason for this numbering order is so that when a bus is carring a binary number, bus[n] is the 2^n weighted bit of the number. This will make more sense when you get to chapter 2. --Mark If you reply to this email, your message will be added to the discussion below: http://nand2tetris-questions-and-answers-forum.32033.n3.nabble.com/4-way-16-bit-mux-tp4031660p4031661.html To unsubscribe from 4 way 16 bit mux, click here. NAML