8Mux16Way

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goo
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8Mux16Way

goo
implementig this by 4Mux16 chips. however getting error msg "a[16] and a[1] different bus widths.
Checked everything, even compared it with chip template cant find mistake. Help.
Is there a list of error messages and their meaning somewhere ?
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Re: 8Mux16Way

ybakos
Do you mean the Mux8Way16 or your own custom chip? Be sure you're wiring 16-bit pins to other 16-bit pins. Hint: the only pins that need sub-busing here are sel.
goo
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Re: 8Mux16Way

goo
I am implementing 8Mux16way using 4mux16way chips that are already done.
i will just give one line of code on which I am getting this error
4Mux16Way(a=a[0],b=b[0],c=c[0],d=d[0],sel=sel[0..1],out=out1);
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Re: 8Mux16Way

ybakos
Ask yourself: how wide is the bus of the Mux8Way16 chip's a input? And how wide is the input of the Mux4Way16's a input?

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Re: 8Mux16Way

cadet1620
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In reply to this post by goo
goo wrote
I am implementing 8Mux16way using 4mux16way chips that are already done.
i will just give one line of code on which I am getting this error
4Mux16Way(a=a[0],b=b[0],c=c[0],d=d[0],sel=sel[0..1],out=out1);
There is no "8Mux16Way" nor "4Mux16Way" chip in the book, so we can only guess at what's happening.

The error message you are getting, "a[16] and a[1] different bus widths," says that you are trying to connect a single wire to a 16-wire bus. The "a[16]" is referring to the a input of your 4Mux16Way chip, the "a[1]" is referring to the single wire that you have selected from the a input to your 8Mux16Way.

You probably want to say "a=a" to connect all 16 wires together.

--Mark
goo
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Re: 8Mux16Way

goo
Firstly my apologies. What I meant was Mux4Way16 and Mux8Way16.
Now I am getting an error on the out1 ( out(1) and out(16) bus width mismatch).
This is surprising since I have implemented Mux4Way16 from Mux16 chips
and that worked well. in that I have used similar code
Mux16(a=a,b=b,sel=sel[0],out=out1);


thanx
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Re: 8Mux16Way

cadet1620
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goo wrote
Firstly my apologies. What I meant was Mux4Way16 and Mux8Way16.
Now I am getting an error on the out1 ( out(1) and out(16) bus width mismatch).
This is surprising since I have implemented Mux4Way16 from Mux16 chips
and that worked well. in that I have used similar code
Mux16(a=a,b=b,sel=sel[0],out=out1);
Think about what is happening on this line. out1 is being created, and internal wires are always created to match the width of the output to which they are connected. The error message says that out1 is a 1-bit bus (a single wire) so it must, therefore, have been created in an earlier statement in the HDL.

I prefer names that are somewhat descriptive; they make it harder to accidentally use duplicate names. I'd name the output from this mux "outAB" or something similar.

--Mark
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