So I have written the following for the ALU. To me logically it seems to work fine yet it fails the comparison chart on 90% of the lines. I don't know whats wrong could someone please point me to my errors so I at least know where I am going wrong. Thanks.
Edit: Implementation removed. Hint: I did this using 1081 Nand gates, yet it can be done with less.
Inc16(in=,out=); //here was my problem
"Negate" is confusing you; it can mean either arithmetic or logical negation. Careful examination of the operation table (fig. 2.6) will lead you to the type of negation you need.
If you didn't already do so, you can replace all the 0s and 1s under zr and ng in the ALU.cmp file with * so that you don't need to worry about the status bits while getting the basic operations working. Be sure to save the original file for final testing.
[Once you get your ALU working, please edit your post to remove the majority of the HDL; we like people to come up with the general structure on their own.]
Hint: I did this using 1081 Nand gates, yet it can be done with less.
For people who didn't follow this, Nicolas is talking about gate count—the number of Nand gates that would result if each of the abstracted chips in his ALU was replaced with its equivalent circuit made of Nand gates.
If you want to do gate counting on your project 3 chips, use 9 Nands for DFF. You will find that the memory chips completely overwhelm the rest of the computer.
Don't get too hung up on optimization. The point is to learn how to use abstraction. A beer inspired and coffee fueled evening and early morning resulted in a 466-gate ALU: Why we like abstraction, but I sure don't recommend this design approach!
Besides, what is optimization for TECS? I've optimized Mux down to 3 lines.
Xor(a=a, b=b, out=x); // (If you turn this in for your Mux,
And(a=x, b=sel, out=y); // your teacher will ask you how it
Xor(a=a, b=y, out=out); // works!)
This isn't too useful, however. Its gate count is high and it's full of hazard glitches.