And Gate malfunction inside DMux8Way Gate?

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And Gate malfunction inside DMux8Way Gate?

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Hello guys. Before I started I must ask for you to be patient with my english (not my native language).

This is my chip:

CHIP DMux8Way {
    IN in, sel[3];
    OUT a, b, c, d, e, f, g, h;



    /*4-Way DMux Gate for abcd*/
    DMux4Way(in=in1, sel[1]=firstbitabcd, sel[0]=sel[0]); //selector= firstbitabcd + sel[0]
    /*4-Way DMux Gate for efgh*/
    DMux4Way(in=in2, sel[1]=firstbitefgh, sel[0]=sel[0]); //selector= firstbitefgh + sel[0]

The console throws comparison failure at line 10. That's where input is set to 1 and sel[3]= 000

I bolded the "malfunction" that I'm seeing in the data flow with both "funny" AND gates. In the case when Sel[3]=000 and in=1, it should be:

a= in (1 in this case)
b= notsel2 (1 in this case, in the previous line I inverted sel[2])
out= should be 1, but it's ALWAYS 0.

In both And Gates, not matter the values of a and b, output is always zero. I have no idea why this happens and this never occurred to me before with any chip. I executed every step of the comparison and both AND gates never outputs 1 when it should (a && b= 1)

This is messing with my chip and affecting the final results because it always feds 0 to inputs of both DMux4Way.

What I'm missing here?
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Re: And Gate malfunction inside DMux8Way Gate?

Simon van Meygaarden
Hi, Jorge;

I am new at this, but I don't mind trying... -smile-

First: I noticed that the two DMux4Way you are using don't have any outputs. That will be a problem, I think.

Second: you are using AND to split the input into 2 signals, one for each DMux4Way, based on sel[2]. But splitting the input into 2 separate signals, that's something we have a chip for, and you've already made it. Why not use that?
If you do, you can use sel[2] as the first selector, each of sel[1] and sel[0] as selector for the DMux4Way, and you're done. Only three chips needed.

If the first two ANDs themselves throw zeroes out, whatever they get in, I can't explain it, but perhaps someone else will.

Take care,
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Re: And Gate malfunction inside DMux8Way Gate?

In reply to this post by jorgeh91
As Simon said, your DMux4Ways don't have any output connections. This means that there are no connections to the DMux8Way's outputs. Your chip will work as soon as you add those missing outputs.

As to the problem you are seeing with the Ands, the HardwareSimulator is known to be buggy when there are unconnected chip outputs. Unconnected outputs on the parts used in the PARTS: section are OK.

Please edit your post to remove the bulk of the HDL. You might want to leave the DMux4Ways and their comments so that there is context for the resposes.