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 This post was updated on . Let's say I have a 2 instruction program: I want to write the value of R0 into the DRegister. Instruction 0: @RO - 0000000000000000 Instruction 1: D=M - 1111110000010000 When instruction 0 is executed the ARegister is "loaded" (by way of a Mux gate) with value 0000000000000000 - as my logic sets the ARegister load bit to 1 when an A-instruction is executed. When instruction 1 is executed the value of ARegister exits the CPU (via addressM) and enters the Memory (via address). How (at the same clock cycle) can the value of 0000000000000000 exit the ARegister via addressM, and then send the value of R0 to ALU via inM so that value of RO can be written to DRegister?
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Re: Behavior of addressM and inM

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Re: Behavior of addressM and inM

 I'd like to take this one step at a time (one paragraph at a time) if that's okay. I'm going to assume that nothing of note is occurring prior to pushing the reset button. I have a question about initial clocks and PC/ROM behavior: it occurred to me that ROM[0] is at the instruction line for the initial 3 clocks. PC spec: if (reset[t] == 1) out[t+1] = 0 Clock 0: I push the reset button... ROM[0] is on the instruction line. PC out is 0 / ROM in is 0 Clock 1: ROM[0] is on the instruction line. PC out is 0 / ROM in is 0 Clock 2: ROM[0] is on the instruction line. PC out is 1 / ROM in is 1 Is this  correct?
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Re: Behavior of addressM and inM

 Administrator How long are you holding the reset HI for? If you hold the reset HI starting some time before the first clock but release it some time before the second clock, then before the first clock we don't know what the value of the PC is, after the first clock it will be 0, and after the second clock it will be 1. If you are asserting the reset synchronously so that it gets asserted as a result of the first clock and deasserted as a result of the second clock, then we won't know what the PC value is either before the first clock or after the first clock (because there hasn't been a rising clock edge WHILE the reset is HI). It will go to 0 after the second clock edge.
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Re: Behavior of addressM and inM

 According to the PC spec: if reset[t] == 1) out[t+1] = 0 Therefore, I know that PC out[t+1] will be 0, but what about PC out[t]? Some value must leave PC at [t] - correct? Thanks so much for the help.
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Re: Behavior of addressM and inM

 Administrator The spec is written (probably for consistency purposes) from the standpoint of a fully-synchronous system. In that case, the signals at a given time are all interpreted as being the signal at a small amount of time after the rising clock edge that happens at time t. As for how a particular simulator applies the reset signal, that's up to the people that right the simulator. They could write it so that the reset signal goes HI at t = -1 and LO at t = 0, in which case the PC would be 0 at t=0 and 1 at 1 t=1. But they might simply apply a signal at t=0 and relax it at t=1, in which case the PC would be undefined at t=0 and 0 at t=1.