There have been several people investigating the Carry Look-ahead Adder, which is a speed optimization over the ripple carry adder that is built in this course. Designers have come up with many other adder optimizations as well.

Another interesting adder structure that trades hardware for speed is called the

*Carry Select Adder*.

The basic idea is to add 2 bits using 3 1-bit full adders and a 2-bit multiplexer. One adder adds the least significant bit in the normal fashion. The other two add the most significant bit, one of them assuming that the carry in will be 0 and the other assuming that the carry in will be 1. Then the multiplexer chooses the output from one of these adders based on the carry produced by the adder for the least significant bit.

This adder gets its speed improvement because multiplexers are usually faster than adders. (CMOS multiplexers are made from

*transmission gates* which are more like switches then logic gates and are very fast.)

CSAs can be cascaded, using longer ripple carry adders, matching the increasing length of the adders to the combined delay through the multiplexers.

The best length sequence actually depends on the relative speeds of the adders and multiplexers.

It's also possible to combine multiple Carry Look-ahead Adders using CSA techniques.

--Mark