There have been several people investigating the Carry Look-ahead Adder, which is a speed optimization over the ripple carry adder that is built in this course. Designers have come up with many other adder optimizations as well.
Another interesting adder structure that trades hardware for speed is called the Carry Select Adder.
The basic idea is to add 2 bits using 3 1-bit full adders and a 2-bit multiplexer. One adder adds the least significant bit in the normal fashion. The other two add the most significant bit, one of them assuming that the carry in will be 0 and the other assuming that the carry in will be 1. Then the multiplexer chooses the output from one of these adders based on the carry produced by the adder for the least significant bit.
This adder gets its speed improvement because multiplexers are usually faster than adders. (CMOS multiplexers are made from transmission gates which are more like switches then logic gates and are very fast.)
CSAs can be cascaded, using longer ripple carry adders, matching the increasing length of the adders to the combined delay through the multiplexers.
The best length sequence actually depends on the relative speeds of the adders and multiplexers.
It's also possible to combine multiple Carry Look-ahead Adders using CSA techniques.
Another interesting adder is the Carry Bypass Adder. This is a combination of ripple carry and carry look-ahead adder. The 8-bit version would use two 4-bit ripple carry adders two 4-bit look-ahead generators that only need to supply the P (propagate) signal. Based on the P signal, a multiplexer selects whether to select the carry in or the carry out of the 4-bit adder to pass on to the next adder. Less hardware, but slower than a full Carry Look-ahead Adder.
Multiple levels of carry bypass can be used in longer adders.
Thanks for posting these. I never thought about using a MUX within an adder, but now I am really keen on the idea. I think I may implement both of these to help further my understanding of the variations possible with adders.
If you have not already found it, you might want to get Logisim. It's a visual logic simulator that will let you see how the various adders work much easier than the TECS Hardware Simulator. The images in my posts are from Logisim.
The various techniques can be mixed to achieve various tradeoffs between speed and circuit size. Here's one using both look-ahead and select.
Hi u have a great design but there is a mistake in ur design ,
u should use XOR gates instead of OR gates
Ex: try adding 12+15 (using or gates) u have wrong answer
try adding 12+15 (using xor gates ) u will have 27
I screwed it up when I was cleaning up the circuit for posting. I'll get a corrected version up later today. FWIW, my original Logisim version tapped the XOR(a,b) from the Full Adders but that would have been harder to explain than showing them outside the adders.