# Condition to logic

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## Condition to logic

 Im currently trying to do mux and I have a really hard time going from out = a if sel == 0 else b Like I cant figure out how to determine whats the value of sel
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## Re: Condition to logic

 Let's start with a simpler problem: create a circuit which has 2 inputs: in and sel and one output out. The output should be equal to in if sel == 1 and to 0 otherwise. What would be the truth table for this circuit?
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## Re: Condition to logic

 in  |  sel |  out0  |  0  |  01  |  0  |  00  |  1  |  01  |  1  |  1On Fri, Apr 3, 2020 at 11:03 PM ivant [via Nand2Tetris Questions and Answers Forum] <[hidden email]> wrote: Let's start with a simpler problem: create a circuit which has 2 inputs: in and sel and one output out. The output should be equal to in if sel == 1 and to 0 otherwise. What would be the truth table for this circuit? If you reply to this email, your message will be added to the discussion below: http://nand2tetris-questions-and-answers-forum.32033.n3.nabble.com/Condition-to-logic-tp4034355p4034356.html To unsubscribe from Condition to logic, click here. NAML
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## Re: Condition to logic

 Ok. And how can you implement this?
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## Re: Condition to logic

 This seems exactly like Nand
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## Re: Condition to logic

 Not NAND really, but quite close. Look at the other gates that you've implemented.
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## Re: Condition to logic

 Opposite of Nand, sorry. probably Nand(a=in, b=sel, out=out1); Not(in=out1, out=out); Maybe?
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## Re: Condition to logic

 Yes, this is called AND gate. I assume you are doing them in the order described in the book, right? Ok, now let's create another gate, with the following spec. it again has two inputs: in and sel, and one output out, such that out = in if sel == 0 and 0 if sel == 1.
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## Re: Condition to logic

 Oh lol. Ok so this is the table: in sel out 1 0 1 0 0 0 1 1 0 0 1 0 But I don't know how to implement it to a gate
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## Re: Condition to logic

 What if you add another column to the table? It's neither input nor output, just intermediate column to help you. It will contain NOT(sel), the negated value of sel. How would that look like? It would be more helpful if you order the table like that: ```in sel NOT(sel) out 0 1 _ _ 1 1 _ _ 0 0 _ _ 1 0 _ _ ```
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## Re: Condition to logic

 This is table I got: in sel NOT(sel) out 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 1 this seems like its Not(in=sel, out=nsel);And(a=in, b=nsel, out=out);
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## Re: Condition to logic

 Yes, exactly! Now you have two gates; exposes its in input when sel == 1 and the other one exposes its in when sel == 0. You need to somehow combine them to produce the specification of mux.