DMux4Way Selector Ordering

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DMux4Way Selector Ordering

wrinklytech
Eventually got this working, with some trial and error and googling etc. Still stumped by why the order of demuxing seems to be critical.

Without publishing code, which I take to be bad form, demuxing sel[0] first then using the outputs to demux sel[1] throws an error, while demuxing sel[1] then sel[0] works. Something similar happens if you do the whole thing longhand, using Nots and Ands.

I hope someone can explain this as I'd like to move on ;-)
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Re: DMux4Way Selector Ordering

cadet1620
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Since you don't mention Mux4Way16, I'm guessing that you got it working and the order for the Mux16s in it makes sense.

Think of the demultiplexors as mirror images of the multiplexors.  If you change the signal flow in the 4-way multiplexor diagram from left-to-right to right-to-left you end up with a demultiplexor.

Since the sel[0] muxes are connected to a-d inputs on the mux, the sel[0] demuxes are connected to the a-d outputs on the demux.

Think about this: if you build a mux out of relays, which are basically electrically controlled switches, that same circuit is a demux!  You just change where you connect the input and output wires.

--Mark
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Re: DMux4Way Selector Ordering

wrinklytech
Appreciate the reply. No I haven't had a go at Mux4Way16, although I can appreciate the concept that a DMux is a Mux in reverse. I imagined the DMux4Way was a less complex task to attempt.
I have a working chip, but don't fully understand way - rather unsatisfactory. I guess I didn't explain my puzzlement with the ordering of the selectors very well :(
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Re: DMux4Way Selector Ordering

cadet1620
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This post was updated on .
Railroad track analogy:
  Train track demux
Outputs a-d, top to bottom.

sel[1] controls the switch on the left, choosing between track pair a and b or track pair c and d.
sel[0] controls the two switches on the right, choosing the select output track.

Note:  hardware bits are numbered right-to-left. In the case when b is selected,
  sel = 01, so sel[0] = 1 and sel[1] = 0.

(This bit ordering will make more sense in chapter 2. When buses are carrying binary numbers, bus[N] is the 2^N bit of the number.)

--Mark
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Re: DMux4Way Selector Ordering

wrinklytech
So the theoretical description

/*
 * 4-way demultiplexor:
 * {a, b, c, d} = {in, 0, 0, 0} if sel == 00
 *                {0, in, 0, 0} if sel == 01
 *                {0, 0, in, 0} if sel == 10
 *                {0, 0, 0, in} if sel == 11
 */

should be read as

/*
 * 4-way demultiplexor:
 * {a, b, c, d} = {in, 0, 0, 0} if sel[1] == 0, sel[0] == 0
 *                {0, in, 0, 0} if sel[1] == 0, sel[0] == 1
 *                {0, 0, in, 0} if sel[1] == 1, sel[0] == 0
 *                {0, 0, 0, in} if sel[1] == 1, sel[0] == 1
 */

That would explain it. I guess I missed the point about hardware bit numbering somewhere along the line!


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Re: DMux4Way Selector Ordering

cadet1620
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wrinklytech wrote
I guess I missed the point about hardware bit numbering somewhere along the line!
You are not alone, many people miss it!

I think that the only place that bit numbering is explicitly stated is in Appendix A section A.4.

It is implicitly shown by the column headers in the truth tables for the 4-way mux and demux.

--Mark
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Re: DMux4Way Selector Ordering

Desmond
This post was updated on .
In reply to this post by cadet1620
I'm a beginner,The chart you provide gave me a great help,Thanks!
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Re: DMux4Way Selector Ordering

cadet1620
Administrator
I'm glad you were able to find help on the forum.

Please edit your post to remove the working HDL. We want people to develop their own solutions.

--Mark
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