I was able to initially implement DMux8Way using 1 DMux4Way gate and 4 DMux gates. However, I am currently trying to understand how the DMux8Way can be implemented using 2 DMux4Way gates. This is coming from the idea that DMux can be thought of as the opposite function of a Mux.
So far, I was able to implement the Mux8Way gate by using 2 Mux4Way and a Mux16 gates. Then I figured, well maybe I can just do a "reverse" implementation for DMux8Way: using a DMux and 2 DMux4Way gates. I tested the chip with this implementation, and it shows that it works.
However, I currently have no clue why this implementation is working. But, I do understand why my initial implementation works (1 DMux4Way and 4 DMux gates).
Can someone possibly explain what am I not getting about this?
Perhaps you'll find it easier to understand this if you visualize this. One way is to draw the diagram on a peace of paper. Another is to use a tool, like logisim.
Start by drawing just a simple DMux and see what happens with the outputs when you play with the inputs. Then draw your implementation of DMux4Way and do the same thing. And lastly, do it for DMux8Way. Do you see the pattern now?