My c-instruction at the highlighted part has '001' for the last three digits. We have agreed that as long as there is no jump, the PC will increment by 1. Yet the correct value is supposed to be 26 for the PC counter, not 1000, which is the value of A-reg. But instruction does have a jump (001 is JGT). Please help me out. Thanks.
Just having a 'dest' component is not sufficient for there to actually be a jump. Remember what it means. JGT means "Jump if the ALU output is Greater Than zero" (i.e., load the PC with the current value stored in the A-register IF the current output of the ALU is greater than 0). The output of the ALU is -1 in your screenshot, so this fails the JGT test and no jump is taken.
I understand that zr (zero or not) and ng (negative or not) in the ALU output will be tested with jjj from the c-instruction to determine whether we make a jump or not. Of course if zr and ng are both zero, we get a positive number.
And I am pretty much stuck here. I just have no idea how I could compare the latter two with the jump bits. Any itsy bitsy clue here in terms of the logic? Do I need ddd bits as well? Thanks.
Let's imagine that we were working with a CPU that had two jump conditions, Fred and Sue.
Fred means to take the jump if output of the ALU is an even number and Sue means to take the jump if the output of the ALU is evenly divisible by sixteen. These are encoded in the instruction using bits 7 and 14,respectively, but only if the instruction is a J-instruction, which is indicated by bit 19 being True and bit 18 being false.
How might we encode this. Well, our top level logic might be:
jump = (Jtype) AND [(jFred AND tFred) OR (jSue AND tSue)]
Jtype means that the instruction is a J-type instruction
jFred, jSue mean that the instruction has those respective jump bits set
tFred, tSue mean that the ALU output passes the tests for a Fred or a Sue jump, respectively
Now we just need to figure out the logic for all of these signals given the instruction and ALU outputs.