How is a first gate implemented in this case the NAND
First post here and self study.
I think I am missing something simple here.
I understand that we don’t have to build the NAND gate as that is supplied, but now I am trying to figure out how to build a simple primitive elementary gate if nothing already exists...
So for example if I wanted to build a NOT gate , but nothing existed like the supplied NAND gate then what would I put in the Parts section ? 🙈
Also what does the supplied NAND gates HDL look like ? Assuming that was build with nothing else to use as well ?
Re: How is a first gate implemented in this case the NAND
This HDL simulator only has two primitive parts that it knows about -- the Nand and the DFF.
The simulator simulates these two parts based on a definition of how they behave.
In reality (as well as in other, more full-featured simulators) you can build both of these out of more basic electronic parts such as transistors. You can actually build either a lot of different ways, but the common way is using MOSFET transistors which act essentially like voltage-controlled electrical switches (at least as they are used in digital circuits).
An N-type MOSFET (NFET) has three terminals -- interchangeable source and drain and a gate. When a high voltage is applied to the gate, it's like closing a switch and connecting the source to the drain. When a low voltage is applied to the gate, it's like opening the switch and disconnecting the source and the drain.
A P-type MOSTFET (PFET) is similar but the opposite polarity. Applying a high voltage to the gate opens the switch while applying a low voltage closes it.
So now imagine taking a PFET and connecting the source to the positive power supply and the drain to the drain of an NFET. Then connect the source of the NFET to the negative power supply. You then connect the input signal to the gates of both transistors and take the output signal from the junction where the drains of both transistors are connected together.
This is how you build a CMOS inverter. When a low voltage is applied the top transistor is turned on and the output is connected to the positive power supply (while the bottom transistor is turned off) and the output is therefore high. When a high voltage is applied the bottom transistor is turned on while the top on is turned off and the output is pulled down to the negative supply voltage.
Most complicated CMOS logic gates are simply additional PFETs and NFETs connected in various series-parallel combinations (or other, more complicated ways, too).