Perhaps slightly off-topic, but I've been poking at a game called MHRD that covers a lot of the same principles... but it also encourages NAND-perfection by automatically counting the NANDs for you in each of your chips and comparing to the global record. (It's what inspired me to make a 4-NAND DMux, 5-NAND HalfAdder, and 9-NAND FullAdder).
I'll try to work-out what I've got going (so far) in my current chipset (and it may illustrate why using the builtin chips becomes necessary after you have a larger chipset... Assuming I'm doing my math correctly... Feel free to call me on any errors....)
If the DFF is basically 2 NAND gates... My Mux can probably be improved but right now is two And, two Or, and a Not for 11 NAND (total 13 per Bit)... a register uses 16 Bits, (so we're [okay, maybe just me] at 208 NAND) for a 16-Bit Register with my chip designs.... Eight of those (total 1664 NAND) plus, per my design one DMux8Way (36 more NAND with my optimized design) and one Mux8Way16 (176 NAND in Mux16, seven in my Mux8Way16 for +1232... our grand total of my design for RAM8 = 1232 + 36 + 1664 = 2932 NAND...)
RAM64 then = 1232 + 36 + (8 * 2932) NAND in my chipset.... or 24,724 NAND....
extrapolating, ~x8 for 512kb ~50,000 NAND...
...and ~x8 for 4096kb ~400,000 NAND...
...and ~x4 for 16Kb = ~1,600,000 NAND just for the main memory.
> 3 million inputs, nearly 5 million I/O lines in total.
Then again, maybe I've mis-managed my calculations... this amazing feat is comprised of ~43,000 transistors (obviously using more optimal gates where possible, but it still makes me doubt my strikingly different calculations....) Check it out: The Megaprocessor
Re: How many transistors would a physical implementation of the Jack computer require?
Okay, that terrible Mux design just had to go.... I don't know why I didn't optimize it further sooner, but the reality of those NAND #'s for memory forced me to act. :) Optimizing my Mux to a 4-NAND design means 6 in a Bit, 96+36+28 in a register (160; down 48 from what I calculated as 208 with the prior Mux chip).
So.... there will still be a "really big" # of NAND to simulate in the entire finished HACK computer.
... 10,812 NAND for RAM64 ....
And apparently I did make an error in the prior calculations... in the conservative direction, though, surprisingly enough. Because my new calculation, for my optimized design, has 2.7 million NAND.... nearly twice as many as I calculated for my less efficient design. And again, that's just the NANDs in the 16Kb of main memory.
Bottom line? Lots and lots and lots of gates.... :)
For CMOS, there is also a transmission gate design. Transmission gates are much smaller transistor count than Nand gates. In this circuit, each Not is 2 transistors and each t-gate it 2 transistors.
http://play-hookey.com/digital/alt_flip_flops/cmos_d_flip-flop.html In most CMOS designs both CLK and not(CLK) are available so that each DFF does not need the clock inverter.
Fantastic! I don't think I could have asked for more! I had been looking at tools like DIA, Multimedia Logic, and TinyCAD to help me visualize the circuits I've been working on. This is definitely next-level. Today I've created my 2-gate-NAND foundation of circuits:
Are all now built in LogiSim, as well as the next tier that I've completed so far:
It's been fun and interesting learning to do these in LogiSim. One project I have at-hand is my 1st PCounter. Being able to draft it here now in LogiSim with my own prefabs should help me wrap my head around it, I think. At the very least, I'll be going through much less paper now, so thanks again! (I note that screenshots of these are also far cleaner than my pen and paper doodles....)