Issue with running hdl in project 01 folder on OSX 10.9.1

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Issue with running hdl in project 01 folder on OSX 10.9.1

robaroy
I'm having a curious issue where my hdl files will not run correctly in the project 01 folder, but it runs perfectly if I save it in project 0 folder and run it.  When run from project 1 folder I'm receiving "Comparison failure line 5."  Here's a screen shot: https://www.dropbox.com/s/ooyizlzyhoogijx/HardwareSimulatorMainScreenSnapz001.pdf
I'm running OSX 10.9.1.  Any ideas on a fix or a workaround?  Should I save all the files needed for project one and put them in the project 0 folder?  I appreciate any help you can provide.
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Re: Issue with running hdl in project 01 folder on OSX 10.9.1

ybakos
Did you implement the Not gate before implementing And?
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Re: Issue with running hdl in project 01 folder on OSX 10.9.1

cadet1620
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The HDL files supplied in the project directories do not have implementations so you cannot use them in other chips until you write their implementations and they pass their tests.

You need to implement the chips in the order presented in section 1.2 — make Not using only Nand, then make And using Nand and Not, then make Or using Nand, Not and And, etc.

You should read the Hardware Construction Survival Kit, it tells you this and other useful information.

--Mark
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Re: Issue with running hdl in project 01 folder on OSX 10.9.1

robaroy
Thank you.  Yes, I realized my mistake.  I thought "And" was first.  Thank you for your quick responses!
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Re: Issue with running hdl in project 01 folder on OSX 10.9.1

tansaku
Thanks for all the replies here.  I'm the instructor on the course that robaroy is taking, and I missed this fixed in a debugging sessions with rob - embarrassing :-)

However I do note that the HardwareSimulator itself gives a very confusing output for an implemented And when the Not is not implemented.  It actually seems to indicate that the builtIn Nand chip is not working.  I was examining the output on the internal pins from the Nand with robaroy and it was giving 1 for all combination of inputs on the internal pin x:

|   a   |   b   |  x  |
|   0   |   0   |   1   |
|   0   |   1   |   1   |
|   1   |   0   |   1   |
|   1   |   1   |   0   |

I wrote a separate test of the builtIn Nand gate and checked that it was working leading to further confusion.  

Clearly reading the documentation thoroughly is desirable, but the challenge with any documentation is remembering everything that has been written.  I had certainly read about that sequencing issue, but did not recall it in my debugging session with rob.

Perhaps there might be some way for the hardware simulator to throw a different sort of error when relying on an unimplemented chip.  Certainly I was very confused by the internal pin output ...

Many thanks in advance
Best regards
Sam Joseph, Ph.D.
Associate Professor
Department of Computer Science
Hawaii Pacific University
Sam Joseph, Ph.D.
Associate Professor
Department of Computer Science
Hawaii Pacific University
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