I have gotten up to Mux pretty smoothly, but the introduction of a 3rd input has left me frustrated. I'm not sure how to even approach this puzzle. I understand (I think) that the the canonical representation of Mux can be desribed:
X(not)YZ(not)+XYZ(not)+XY(not)Z+XYZ  Is this starting off point correct? (4 Nots, 8 Ands, 3 Ors) Up till now, all the Parts have been with 2 inputs that Nand and others have in its parameters. Can Nand, Not, And, Or, and Xor have more than 2 inputs intrinsically? In the Mux template there are 3 inputs, just having trouble on how to reconcile that with what up until now has been limited to 2 inputs. During the Test, how is the third input incorporated if all the parts accept only 2 inputs? Any guidance is sincerely appreciated. 
Administrator

Your canonical expression for Mux is correct, but it would be clearer to use the actual signal names and write it as out = a b sel + ~a b sel + a ~b sel + a b ~sel. Search the forum for "Karnaugh map" to learn about a tool that can help you simplify the canonical expression. Suppose that you want to write a 3input And gate. It will have three declared inputs INPUT a, b, c; And the HDL that implements out = (a b)c would be And (a=a, b=b, out=ab); And (a=ab, b=c, out=out); The And.tst script would have lines in it like set a 0, set b 1, set c 0, eval, output; that manipulate the 3 inputs to the chip. Mark 
Thank you for the reference to the Karnaugh map, and shining a light on how to develop 3+ input gates. Just so that I know I am going in the right direction, what is the minimum number of gates required for Mux? I was able to do it with six (using Karnaugh wiki), but something tells me there is a way for it to be simplified further. If that is the case, and I continue to use sub optimal implementation, will it gum up the works in future projects?

Administrator

Suboptimal implementations are not a problem. You do the projects in independent subdirectories so that each project uses the builtin version of chips from earlier projects. It is possible to copy your project 1 HDL files into project 2, but this will not work for project 3 because the RAM chips get huge in a hurry and the simulator runs out of memory.
You can get the Mux down to 4 gates, but don't worry about optimization now. It's more important to get everything working first. After you have more experience you can revisit your earlier work and optimize. Hint: although it's possible to design Mux4Way using canonical form and Karnaugh maps, it's a much smaller implementation if you figure out how to build it using multiple Mux parts. Mark 
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