# Mux chips work but...

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## Mux chips work but...

 Hi every ones!, First of all, A super giant thank you for the existence of this book, I was looking for this kind of teaching since a while... I started reading that book, one week ago. I’m currently building all the (chips/gates) of the project 01. Til now I build those one : -And.hdl -And16.hdl -Not.hdl -Not16.hdl -Or.hdl -Or16.hdl -Mux.hdl *******The problem(interrogations) that i have with the last one(Mux) is that it take me a long time to figure out how to do it, and I have the impression that even if this gate work, that i don’t understand it. After a few minute of trying without success, OK a few hours! :P, I re-reed the chapter til "the canonical representation" explanation. This read I though, bring me to a upper understanding level :). So I draw the boolean logic of the Mux: a | b | sel | out ------------------ 0 | 0 |  0  | 0 ------------------ 0 | 1 |  0  | 0 ------------------ 1 | 0 |  0  | 1 ------------------ 1 | 1 |  0  | 1 ------------------   0 | 0 |  1  | 0 ------------------ 0 | 1 |  1  | 1 ------------------ 1 | 0 |  1  | 0 ------------------ 1 | 1 |  1  | 1 ------------------ Base of my understanding of the canonical representation, I only the (out === 1) scenario, and do the canonical representation of it (out === 1)           ---------------     a   b     s     out 1 | 0 |  0  | 1 1 | 1 |  0  | 1 0 | 1 |  1  | 1 1 | 1 |  1  | 1 canonical representationa,not(b),not(s) + a,b,not(s) + not(a),b,s + a,b,s After that, I build my chip and execute the testing with success. My understanding that what I did can be compare as a key looker, the canonical representation is all the different key format possible to unlock the door. The problem where Im not sure and the reason of this postOnce I see the success, I decide to compare my Mux.hdl, with another one that I found on Git-hub, Mine have 14 gates totals:-3 not gates -8 and gates -3 or   gates The one I found (4 gates total) -1 not gate -2 and gates -1 or gates So, now I’m confuse, Doest my success with the Mux gate was purely lucky, Do I misunderstood something about the canonical scenarios. I have the feeling that they are some way to optimise canonical representation to pass from 14 to 4 gate but I dont know how :S And I don’t want to continue my read of the book til I don’t have a full understanding of this concept. So if someone could refer me to a (post/book/article etc.) that will be super appreciate :) Thank a lot and sorry for my poor English and the super long text :)
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## Re: Mux chips work but...

 Administrator j.f.nault wrote Mine have 14 gates totals:-3 not gates -8 and gates -3 or   gates The one I found (4 gates total) -1 not gate -2 and gates -1 or gates So, now I’m confuse, Doest my success with the Mux gate was purely lucky, Do I misunderstood something about the canonical scenarios. I have the feeling that they are some way to optimise canonical representation to pass from 14 to 4 gate but I dont know how :S And I don’t want to continue my read of the book til I don’t have a full understanding of this concept. So if someone could refer me to a (post/book/article etc.) that will be super appreciate :) Thank a lot and sorry for my poor English and the super long text :) You did very well learning to use the canonical representation to engineer a solution for the Mux; it was not luck. One of the better tools to use to simplify canonical representation is called a Karnaugh Map.  Search the forum and you will find several references. This might be a useful post. You will also want to learn a bit about Boolean Algebra. It is like arithmetic algebra but for logic. The rules are similar, but not quite the same. A very powerful rule is called DeMorgan's law. Another important observation that you made was the "key in the door".  Another way to think about And gates is exactly that.  Rename the inputs in and key and then the function of the And gate is in->out if key is True and out=False if key is False. --Mark