would like to know if its a right way to build this chip, i've seen the the suggested and correct way is using the mux chip we build earlier 16 times (0...15) but can i stick with my way as well?
thanks for the answers
There are multiple ways of doing most of the parts. Any solution that behaves according to the specification is a correct solution.
Have you tested your solution to see if it behaves properly? If so (and if the tests you good enough), then it is correct.
The suggested solution is simply emphasizing using increasing layers of abstraction as you go from primitive to complex logic structures. This approach emphasizes the simple parallelism involved, which is masked by the limited expressiveness of this HDL. In some schematic capture programs you could implement the Mux16 with a single Mux part in which the signal names used imply the needed parallelism.