It seems you are overcomplicating things with additional parts. I have solved it using 3 Mux16s and nothing else.
Think about the inputs as two groups, it helps to visualize them in binary.
a is 00
b is 01
c is 10
d is 11
The 1st bit seems to break the inputs into two groups, and 0th bit selects single input from each group... Can't say much more than that (:
Selecting b doesn't work in your design, because b is selected when sel = 01, 0 or 1 is 1, so top mux selects b, but the right mux selects the input from bottom mux (since it uses sel), which doesn't interact with b in any way.
What is your logic behind your solution? I'm finding it hard to follow.
Thank you for your reply. I do understand that this can be made with 3 Mux16s - I found this out after much frustration with my solution not working. But in order to try and further my knowledge I'd like to find out why my solution fails?
If you look at my truth table I hope you'll understand my logic. The Or gate decide the first M16 chip to pick either the a bus or the b bus. With only 00 giving a as the output.
The And gate decides if the second M16 chip picks c or d. With only 11 favoring the d bus.
The third Mux16 then has to decide between the output from the abMux or the cdMux and it does this using the sel value. Unless I've really messed up I can't see how my logic dosn't work. I understand it isn't efficient - but it should work?