# Nand Implementation

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## Nand Implementation

 I'm having trouble understanding how Nand would be implemented.  My problem is every way i try to do it is a paradox, Not and And are both created from Nand, yet Nand contains in itself both Not and And.  Can anyone please explain to me how Nand is actually created in logic?
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## Re: Nand Implementation

 Administrator James wrote I'm having trouble understanding how Nand would be implemented.  My problem is every way i try to do it is a paradox, Not and And are both created from Nand, yet Nand contains in itself both Not and And.  Can anyone please explain to me how Nand is actually created in logic? From a mathematical point of view, Nand is an axiom, something that must be assumed to exist. In the case of hardware, the way the electronics works out the inversion is built in to the primitive gate. This diagram shows a CMOS Nand gate (left), Not gate and And gate (right). The Not gate is just a 1-input Nand, and the And is a Nand followed by a Not. (This drawing was done with Logisim.) --Mark
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## Re: Nand Implementation

 Thanks for the quick reply but im still having trouble understanding those diagrams cause i just have some amateur coding experience and no electrical engineering experience.  Do you think you could explain step by step whats going on in the nand gate in lay terms? Or refer me to a text i can read about the diagram?
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## Re: Nand Implementation

CMOS ICs are made using Field Effect Transistors. FETs come in two varieties, p-channel and n-channel.

P-Channel FETN-Channel FET
 source gate drain
 source gate drain

Simplified for this discussion, the p-channel FET only turns on the connection between the source and the drain when the gate is low voltage. The n-channel FET only turns on when the gate is high voltage. Otherwise, there is no connection between the source and the drain.

First I'll describe how the Not works. The upper transistor is a P-FET with its source connected to power (+5V) and the lower transistor is an N-FET with its source connected to ground (0V). Both transistors' drains are connected to the Not's output.

When the input to the Not is low, the P-FET is turned on and the N-FET is turned off. The output is only connected to +5V. When the input is high, the P-FET is turned off and the N-FET is turned on. The output is only connected to 0V.

The And also has P-FETs connected to power and N-FETs connected to ground. The P-FETs are connected in parallel and the N-FETs are connected in series.

When either of the inputs is low, one or both of the P-FETs is turned on and one or more of the N-FETs will be turned off. The output is connected only to +5V. When both inputs are high, both P-FETs are turned off and both N-FETs are turned on. The output is only connected to 0V.

Think about this: what happens if we vertically mirror the geometry of the Nand gate so that there are series connected P-FETs on top and parallel connected N-FETs on the bottom? It turns out that it's as easy to make Nor gates as Nand gates in CMOS.

--Mark