Nor gate

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Nor gate

Matt Keenan
I realise that in hardware Nor gates aren't used as much as Nand gates. Although I only have passing knowledge of electrical engineering my impression for the reason for less use of Nor gates was that the slew rate of a p gate was quicker in parallel on a rising signal and the slew rate for a n gate was quicker on a falling signal; hence Nand gates are quicker than Nor gates. Having said that there are times when using a Nor gate is justified as it might save from using a more complex gate structure than using just Nands and Nots and hence have a faster overall slew rate for the whole. On that basis is it possible to get a Nor gate added as a builtin? In furtherance of this, I have added a repo to github for this simple patch;

https://github.com/mattkeenan/nand2tetris.git
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Re: Nor gate

cadet1620
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This slight speed advantage of Nand over Nor only applies to CMOS, where it's easy to make both Nand and Nor. 30+ years ago when I was learning all this, the most prevalent logic was TTL which only had N-input Nand as its primitive gate, and if you needed very high speed you used ECL which only had Nor. Who knows what the world will look like 30 years from now.

For the purpose of the Nand2Tetris course, I think that adding a Nor built-in as an alternate primitive gate would just add confusion. In my Hack Computer there are only two instances where I have an Or followed by Not, so I also don't think that it's justified to add Nor to the list of Project 1 synthesized gates.

Real world hardware implementation is also not a concern of this course. For instance, nobody implements Xor on an IC using Nand/Nor; nor would they implement Or8Way using a tree of 2-input Ors.

If you haven't already found it, you sound like you might enjoy Logisim, a schematic based logic simulator that's powerful enough to build a hack-like computer.

--Mark
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Re: Nor gate

Matt Keenan
I agree that the topic is indeed too large to dive into on a whim, but I figured it would be easy enough to add the primitive. I am somewhat aware of the optimisation tricks like 6 transistor Xor gates and multiway gates using either 2n or 2n+2 transistors. You could easily design a CPU with predominately Nor gates rather than Nand, my point is you should explain the preference for Nand over Nor even if it is a one sentence hand wave; then it provides a student with an easy gateway to further learning if they chose to go further down the rabbit hole.