PC Chip Kinda Works..

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PC Chip Kinda Works..

Butters9000
I'm missing the big picture.  Below is my out.  The compare clearly states that out = 0 @ 1+.  I don't understand why it should be.

Output:

| time |   in   |reset|load | inc |  out   |
| 0+   |      0 |  0   |  0   |  0  |      0 |
| 1     |      0 |  0   |  0   |  0  |      0 |
| 1+   |      0 |  0   |  0   |  1  |      1 |
| 2     |      0 |  0   |  0   |  1  |      1 |

Compare:
| time |   in   |reset|load | inc |  out   |
| 0+   |      0 |  0   |  0   |  0  |      0 |
| 1     |      0 |  0   |  0   |  0  |      0 |
| 1+   |      0 |  0   |  0   |  1  |      0 |
| 2     |      0 |  0   |  0   |  1  |      1 |

I think I'm doing things in right priority as I seen suggested in other threads.
Based on the compare file, out should not equal 1 immediately after inc is set.  It would appear that out changes to 1 @ time =2.

My first problem is that I don't understand what the N+ are vs the N's.  Its almost like the N+'s are half steps.

_tb






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Re: PC Chip Kinda Works..

cadet1620
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Butters9000 wrote
Based on the compare file, out should not equal 1 immediately after inc is set.  It would appear that out changes to 1 @ time =2.

My first problem is that I don't understand what the N+ are vs the N's.  Its almost like the N+'s are half steps.
You've got the right idea about N+. It's what's happening between clock ticks.

Since 'out' is changing without a clock tick, I suspect that PC's 'out' is connected somewhere on the input side of the Register in your HDL rather than directly to the Register's 'out'.

If you want to, you may email me your HDL and I'll take a look at it.

--Mark
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