# Physical implementation of NAND and DFF primitives

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## Physical implementation of NAND and DFF primitives

 Hello all, I am about halfway done with the Nand 2 Tetris course, and I'm enjoying myself immensely. For a long time, I have wanted to understand "the full stack" with regard to computers, and the textbook by Dr. Nisan and Dr. Schocken has made that goal attainable. Many thanks to them for their work. The textbook shows that an engineer can construct a computer by creatively and intelligently arranging a small set of primitive parts. To my mind, the most important of these primitives are the NAND gate and the Data Flip Flop. If you start with just these two parts, the book will show you how to arrange them into the building blocks necessary to build a functional computer. (The NAND gate is introduced on page 11, and the DFF is introduced on page 42. Also see page 19, where the authors reveal the fascinating fact that any logic gate can be constructed using only NAND gates!) Because the book assumes that these primitives are already available to a hypothetical computer engineer, it does not go into detail to describe how they are implemented. I decided that I wanted to know how these parts were built in the physical world! Through much trial and error, over the course of about six weeks I was able to contruct a working NAND gate and DFF. I even added an "enable" multiplexer to the DFF to make it a 1-bit register. (See page 43.) I did not use any pre-packaged logic gates in this project; I used only wire, switches, LED's, batteries, resistors, and NPN transistors. I've uploaded a video to Youtube showing my circuits in operation, as well as my circuit diagrams. I hope this will be interesting and useful to many of you. Enjoy! https://www.youtube.com/watch?v=8O68_Ovw6j4
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## Re: Physical implementation of NAND and DFF primitives

 Administrator Congratulations.  That's impressive work. --Mark
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## Re: Physical implementation of NAND and DFF primitives

 Thanks very much! I certainly learned a lot.
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## Re: Physical implementation of NAND and DFF primitives

 Administrator If you are running Windows, you can get a free schematic editor at     http://expresspcb.com/ExpressPCBHtm/Download.htmYou also get a free PCB layout tool.  (Their intent is that you design your PCB and have them build it...) Took about a minute to draw your Nor.     Quite handy if you are going to be doing more electronics development. --Mark
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## Re: Physical implementation of NAND and DFF primitives

 Wow, that's really neat. I suppose you could prototype on the breadboard, and then use Express PCB to make your circuit permanent.
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## Re: Physical implementation of NAND and DFF primitives

 Administrator This post was updated on . I just used the PCB layout program to play around; I've never had one built.  For work, my hardware engineer partners do the layout using professional tools and we have the boards built by regular board houses. I love playing around with breadboards, especially using them with kids to introduce them to logic ICs. Here's an adding machine one of my students built.     One of the buttons clears the accumulator and the other one adds the number on the switch to the accumulator. For those who are curious, here's the schematic:     adder.pdf--Mark
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## Re: Physical implementation of NAND and DFF primitives

 Very, very cool. I'd be interested to look at a diagram of that adder if you have one easily accessible. So do you teach, or do you do engineering work? You mentioned your hardware engineer coworkers, but then you mentioned a student, so that threw me for a loop. :)
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## Re: Physical implementation of NAND and DFF primitives

 Administrator I'm an independent contracting firmware / embedded systems programmer.  I also taught high school math to gifted middle school kids for several years (until the school went bankrupt, alas). I'll add the schematic to the post with the picture. --Mark
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## Re: Physical implementation of NAND and DFF primitives

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## Re: Physical implementation of NAND and DFF primitives

 Here's the schematic and eagleCAD layout of the DFF primitive. Transistor T1 is the data inverter. Transistors T2 and T3  NAND the clock with either D or /D Transistors T4 and T5 are the cross coupled pair that form the flipflop - and produce the outputs Q and /Q Whilst it looks a lot of components, especially all those double diodes, by using surface mount parts, this reduces to a board area of 1" x 0.75"
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## Re: Physical implementation of NAND and DFF primitives

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## Re: Physical implementation of NAND and DFF primitives

 Administrator Cool project! You can save a few transistors per slice in the ALU by inverting the control signals. Move the 'z*' inverters to the instruction decoder so there are only 3 transistors instead of 3 per slice. If you invert 'nx' and 'ny' in the instruction decoder, then you can eliminate the output inverter in the "zero" circuit. (Your conditional inverter is an Xor: !a xor b == a xor !b.) I don't see any mention of the ALU's 'zr' status bit.  You can add a ripple zero detect to your ALU slice: Zout = Zin & !out.  I think transistor count will be the same as an external 16 bit zero detect, but it might be better mechanically.  (Ripple delay shouldn't be a problem since its ripple occurs in parallel with the adder's.) --Mark
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## Re: Physical implementation of NAND and DFF primitives

 Hi Mark Thanks for the tips. I'll look and see if  I can save transistors in the instruction decoder stage. Back in the mid 1960's when transistors cost today's equivalent of \$10 to \$50 it was important to save every last one - thus the amazingly minimal design of the PDP-8.   1400 transistors and 10000 diodes. If you could make the logic work using diodes, and save a transistor here and there - DEC would do it. However, these days, high speed switching transistors (eg MMBT2369L) are just 5 cents, likewise with high speed schottky diodes. So the design exercise should be put into creating a good DTL NAND  (high speed, good fan-out, low power) rather than saving down to the last transistor. Likewise with the DFF. It has to be high speed and free of race conditions and glitches. Get these two building blocks right - and you have a good DTL computer. Amazingly - someone is reverse engineering the PDP-8 logic  modules and offering these designs as EagleCAD board and schematics. What a dedication  to the art. http://svn.so-much-stuff.com/svn/trunk/Eagle/projects/DEC/Rxxx/R211/R211X.pdfWill keep you informed with any progress.  I'm 50 this year - and looking at this as a retirement project. Ken
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## Re: Physical implementation of NAND and DFF primitives

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## Re: Physical implementation of NAND and DFF primitives

 Hi All, I have looked more into producing a module that provides the basic building blocks for the N2T design. I have increased the transistor count from 10 to 12,  with the additional transistors providing the pair of cross-coupled NANDS, as used in the DFF.  This gives much better flexibility - and allows the module to be more easily configured as a DFF, or more correctly a single bit register. The module has jumper links to allow the various configurations to be set.   Anticipated configurations will be: 1.   Full Adder  (or 2 half adders) 2.   2  XOR   (signal negaters) 3.   2  two input MUX 4.   DFF  plus loading MUX 5    Various combinatorial gates, inverters etc. I have included a LED on the Q output of the DFF - with a suitably slow clock frequency, this can be used for display or diagnostic purposes. I am also planning a pin compatible module that uses standard 74HC00 Nands instead of the DTL.  This would allow improved performance, cleaner signals, and a lot less construction involved. I plan to have a small batch of pcbs manufactured to test the performance of the DTL design. Ken
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## Re: Physical implementation of NAND and DFF primitives

 That is fascinating work, Monsonite. Please do keep us updated on any progress. Do you have any plans to implement on-chip memory, or do you think the Arduino is the best way to go?