Problem with the first Mux In diagram 5.8 of a CPU
In order to build a CPU chip , i am starting with instruction decoding , so the first thing is to determine the type of instruction , if the coming instruction is an A-Instruction ( i = 0) it should be loaded into the A Register , or if it is a C-Instruction (i = 1) they are not loaded , and these trick is doing by the first Mux in the diagram on the book of the CPU , this Mux must chose either an instruction or an out ALU , i think that the sel bit of this Mux must be the i bit of the Instruction , but the entries a,b of the Mux is in opposite order with i bit of instruction , so i don't found any solution , i need a help
Re: Problem with the first Mux In diagram 5.8 of a CPU
In a schematic like the CPU diagram, where the multiplexor inputs are not labeled, the only thing the at mux symbol tells you is "a choice is made based on the select value".
You have correctly identified the select signal, and you know which input signal needs to be selected when 'i' is 0, so that is the signal that needs to be connected to the 'a' input.
(On engineering schematics you will often see names d0-d3 instead of a-d (on 4-way mux) or just the numbers 0-4. Very often, only one of the inputs at one end or the other is labeled 0 and the remaining inputs are then 1-3, in order.)