[There have been some recent questions about race glitches and propagation delay on the Coursera forum, and I remembered that I had a nice timing digram somewhere on my work computer...]
A while ago, as part of a Verilog refresher (I was going to need to add some functionality to an FPGA in one of my customers' products), I wrote a Verilog implementation of the Hack Computer using the suggested design hierarchy and the most common student designs for the parts. I also implemented DFF in Nands, using the classic cascaded SR-latch design.
Here's a timing diagram from that computer. It shows how messy the signals can get when propagation delay is added into the simulation.
This is a trace showing the execution of one instruction. The simulated Nand gate delay is 1 nanosecond (ns).
The instruction being executed is M−1;JGT, with the data value 0x0001 being read from memory. This is a bit of a nonsense instruction, but it exhibits maximum computation and jump detection delay.
The upper blue traces are the Computer's inputs, outputs and Registers.
What's Happening When
How Fast Can the Computer Run?It appears that the clock for the next instruction could occur any time after the logic settles; as soon as t+167 which would yield a maximum clock speed of 5.98 Mhz. However, there are some things that need to be taken into consideration.
The first thing is the setup time for the DFFs. Setup time is how long the inputs must be held valid before the clock triggers. For the Master-Slave DFFs this is 2 Nand delays. In the real world, random extra delays like the lengths of interconnecting wires mean that we can not design for exactly 2ns setup time; the clock should be at least 3ns after the logic settles.
More important is that the simulation can not be assumed to be an accurate reflection of the real world. There may be bugs in the design of some of the simulated parts (It is not possible to simulate the RAM and ROM to the Nand gate level because there would be about 4.5 million in the RAM.) And there may be data patterns that were not considered that cause slightly longer delay.
Also, beyond what the simulation tells us, we need to consider how much variance there is in the manufacturing process for the parts used to build the computer. The delay times may vary noticeably from lot to lot. The manufacturer's specs will tell us what to expect.
Designers need to include a safety margin beyond the calculated worst case timing to handle unexpected changes during production. In this timing diagram, the margin is (34−3)/200, about 15%. (200ns was a convenient round number.)
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