I did a bit of Verilog work a few years back and when specifying inputs to a gate, one could simply specify a 0 or 1 -- they are effectively a true/false constant. Is something similar possible in Nand2Tetris style of HDL? For instance, could one specify the AND gate as:
IN a, b;
Nand(a=a, b=b, out=nout);
Nand(a=nout, b=1, out=out);
Notice the 'b' input on the second Nand is simply tied to 1.