[Ram64+] So it doesn't really matter which bits of 'address' you use to select the ram and which bits send on as the internal RAM's 'address', right?

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[Ram64+] So it doesn't really matter which bits of 'address' you use to select the ram and which bits send on as the internal RAM's 'address', right?

ppfvy
Sorry if my title isn't clear. I keep getting mixed up over whether address[0] or address[n-1] (on an n-bit address) is the most significant bit. I know this is in the HDL spec somewhere, but instead of finding it I took a guess and used address[0..2] to select between the RAM8s and address[3..5] to send as the address for the gate, and it worked fine. Then I tried the reverse - that worked fine too! I guess if you use the LSBs to select between the RAMs they will have a goofy internal state, but still store and return the right values for the given addresses.

Further, as far as I can tell (though I haven't tested this), you don't even need to be consistent between the different RAMs - a RAM64 could use bits [0..2] to select between the RAM8s, and a RAM512 that uses it can use bits [5..8] to select between the RAM64s. I'm sure this is horrible practice, but as long as each chip is consistent internally (i.e. it uses the same bits to select the RAM as it uses to select the output), it seems like you could even do something crazy like use 3 bits in the middle of address to chose the ram and send the beginning and end bits as the address.

I'm not sure this is even worthwhile to post, just thought it was interesting - you can seemingly end up with the same random-access characteristics from RAM with a totally mixed up internal state, unless I missed something.
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Re: [Ram64+] So it doesn't really matter which bits of 'address' you use to select the ram and which bits send on as the internal RAM's 'address', right?

cadet1620
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ppfvy wrote
I'm not sure this is even worthwhile to post, just thought it was interesting - you can seemingly end up with the same random-access characteristics from RAM with a totally mixed up internal state, unless I missed something.
This is a legitimate question, and worth a bit of discussion 8-)

At this level of abstraction, it doesn't matter where in which sub-RAM/Register the words get stored, as long as there is a one-to-one mapping of addresses to storage locations. The mapping doesn't even need to be consistent between the sub parts. For example, consider this, with address[3..5] used to select between Ram8s:
    RAM8(address=address[0..2], ...);
    RAM8(address[0]=address[0], address[1]=address[2], address[2]=address[1], ...);
    RAM8(address[0]=address[1], address[1]=address[0], address[2]=address[2], ...);
    RAM8(address[0]=address[1], address[1]=address[2], address[2]=address[3], ...);
    ...
That's a whole lot of typing for no useful gain!

There can be a reason to use some of the low-order address bit to select between physical RAM chips.

Consider an architecture that allows byte, word, and double-word access to RAM. In this case one might want to use address[0..2] to select the internal sub-parts. This is called interleaving.

The data buses would be 32 bits wide and the memory system would have a control circuit that would allow parallel access to up to four 8-bit wide RAM chips in a single memory cycle.

--Mark
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