SR Latch Building

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SR Latch Building

vishparshav1
This post was updated on .
I have been trying to write HDL for SR Latch. The HDL code is as follows:
CHIP NorLatch
{
        IN s,r,q,qnot;
        OUT q,qnot;
        PARTS:
        Nor(a=r,b=qnot,out=q);
        Nor(a=s,b=q,out=qnot);
}

-------------------------------
the latch is normal nor gate latch.
I wanted to have a feedback loop of the outputs but cant do this as simulator issues an error when i try to load this. The error is :
Line 6, Cannot connect gate's output pin to part.


Can somebody please help me building this latch.How to get the feedback loop.
I know that there is a build in DFF present but i want to build my own so plz help me asap.
You can write a mail to me on vishparshav1@gmail.com or reply here.
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Re: SR Latch Building

cadet1620
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The Nand2Tetris hardware simulator cannot handle asynchronous feedback, only feedback using the built-in DFFs.

To experiment with non-synchronous sequential circuits, I recommend Logisim.

--Mark
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Re: SR Latch Building

vishparshav1
So i would have to use the built in dff cant build my own ?
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Re: SR Latch Building

vishparshav1
In reply to this post by cadet1620
n thnk u logisim is great
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