Don't spend much time on optimizing Nand gate count. Gate count optimization is important if you are designing ICs, but the exact optimization varies. For some types of ICs Nand gates are fundamental. For others it's Nor. For CMOS it's often easier to use "transmission gates" which are more like switches than Boolean logic. For some, extra inputs are almost free, so a 4-input Nand is only slightly larger than a 2-input Nand.
If you are optimizing ICs for speed, very often you use more gates to achieve shorter signal paths.
There are also timing considerations that need to be dealt with. For instance, your 4 Nand Mux cannot be used in real hardware because it has a hazard glitch.
For this course, try to think about abstraction and encapsulation. For instance, making DMux8Way from 3 narrower DMuxes is preferred, although it results in higher gate count.
Synchronized Not, actually. It's a way to use the TECS hardware simulator as a logic analyzer.
Propagation delay caused problems are a plague. One generally doesn't learn much about them beyond hazard and race glitches in school. He learns about them on the job when they crop up in his designs and he has to debug them.