# Simplifying chips

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## Simplifying chips

 In discussions Xor is always represented with these parts     Not(in=a, out=nota); (1 Nand)     Not(in=b, out=notb); (1 Nand)     And(a=a, b=notb, out=w1); (2 Nand)     And(a=nota, b=b, out=w2); (2 Nand)     Or(a=w1, b=w2, out=out); (3 Nand) I found     Nand(a=a,b=b,out=naab);     Nand(a=a,b=naab,out=w1);     Nand(a=naab,b=b,out=w2);     Nand(a=w1,b=w2,out=out); 4 against 9 As i went on with the course Mux 4 against 8 HalfAdder 5 against 6 (with Xor 4 Nand) else 5 against 11 FullAdder 9 against 13 (with my halfadder) else 9 against 15 or even 9 against 25 (Xor) At what point do i stop simplifying these chips?
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## Re: Simplifying chips

 Administrator Don't spend much time on optimizing Nand gate count. Gate count optimization is important if you are designing ICs, but the exact optimization varies. For some types of ICs Nand gates are fundamental. For others it's Nor. For CMOS it's often easier to use "transmission gates" which are more like switches than Boolean logic. For some, extra inputs are almost free, so a 4-input Nand is only slightly larger than a 2-input Nand. If you are optimizing ICs for speed, very often you use more gates to achieve shorter signal paths. There are also timing considerations that need to be dealt with.  For instance, your 4 Nand Mux cannot be used in real hardware because it has a hazard glitch. For this course, try to think about abstraction and encapsulation. For instance, making DMux8Way from 3 narrower DMuxes is preferred, although it results in higher gate count. --Mark
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## Re: Simplifying chips

 In reply to this post by Koen_Be3840 I get it  (DFF + Not = SNot SafeNot?) Thx Marc
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## Re: Simplifying chips

 Administrator Synchronized Not, actually. It's a way to use the TECS hardware simulator as a logic analyzer. Propagation delay caused problems are a plague.  One generally doesn't learn much about them beyond hazard and race glitches in school.  He learns about them on the job when they crop up in his designs and he has to debug them. --Mark
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## Re: Simplifying chips

 In reply to this post by Koen_Be3840 One last Q about this Mark In the example:     Hazard Glitch - sel and !sel both low for an instance     Race Glitch - a running ahead of sel Why is the HG fixed in the example and the RG is not?