I gave the chapter 4 lecture yesterday, and I found the diagram on slide 14 of the presentation a bit disingenuous. It shows the A register connected directly to the address lines of the ROM, to demonstrate that the A register controls the jump destination.
It would probably be better if the diagram showed the A register connected to the PC, whose load and increment lines were controlled by some logic, and the PC's output connected to the address lines of the ROM. This would show more clearly that the A register is loaded into the PC only on jumps, and the PC's value controls the next instruction to fetch.
You are absolutely right. The figure is misleading. Unless you read it "conceptually", but that's a weak defense. The good news is that in Chapter 5, which describes how to connect the various chips together (e.g. A to PC to ROM), the figure are accurate (I think). Thx for the bug report! -- Shimon