My students are currently building the ALU. We are seeing two errors that we are not sure how to handle. We are trying to use the most significant bit of the output as an input to an And gate and it gives error about connecting gate's output pin to part. If we change the name of the output so that it is not the final output to the ALU, then the error changes to something regarding a sub bus on an internal node. I'd like to show the code, but do not want to publicly post anything related to a solution. I could email someone the code if they are willing to take a peek.
Section A.5.3 specifies how to handle buses and sub-buses. The convention in this HDL is that you can connect to arbitrary sub-buses of chips that you use (even with overlap), but that "pins" can not be sub-bused.
Example: suppose that you have a chip "C" with a 16-bit output bus that you want to connect to a 16-bit pin called sum, but also to use the 7th bit to connect to a 1-bit pin called f, then you simply write:
In retrospect we should have allowed internal pins to be sub-bused too. Our original reasoning was one of minimality: we are thinking of the internal pins as logically "atomic" within the chip, and this suffices since any pin of an internal chip can be partitioned at will into whatever desired atomic internal pins.
Sarfraz, recall that the Mux16 has only two inputs: a and b. You are specifying that Mux16 has 4 inputs, a - d. You can also simplify your HDL. Since the Mux4Way16 inputs and outputs are 16 bits, and the Mux16 has 16 bit inputs and outputs, you can write a=a and out=out1, etc.