So, I was able to successfully implement the no-stat part of the ALU as well as ng (just take a look at the last bit :)). Now I'm trying to build the logic for the zr part, and this is what's confusing me.
I think I can explain this generally without the need for posting my code.
So, I've connected a couple sub-buses to the output of my Mux gate (the one that outputs out and no). Each sub-bus is run through a specific gate designed to handle 8 bits, and then the two outputs are put through one more gate (I'll call this output zr3) before I finally output zr.
I'm confused why this isn't working. Based on my output and the compare file, it looks like I need to negate zr3 before I output zr. Why is this the case?
Thanks in advance. I'm happy I've at least gotten through the meat of this exercise.