I've tried to count the number of NAND gates in the different chips.
The numbers reflect my unoptimized solutions.
While the cpu takes 3578 nands,
the ram8_16, (8x16=128 bits), takes 2618 nands.
I would like to get some feedback about where my nand count could improve.
Counting the number of 2-input Nand gates used in a nested implementation like the one done for N2T only gives an indication of how quickly the complexity grows as higher level parts are built. It's not something that would be optimized.
Real world implementation is not done with just 2-input Nands. For instance CMOS, which is the most common logic family these days, can implement Nor for exactly the same cost as Nand, as well as a transmission gate which is like a controlled switch. Signals can flow either direction in a transmission gate which allows for some very strange optimizations.
For example, a Mux can be made in CMOS with a Not and 2 transmission gates.
Also, under the digital logic level, all this is implemented using transistors which are analog devices. Some circuits can take advantage of this to do optimizations that are "magic" as far as the digital world is concerned. This is particularly true of memory devices. Only the smallest and fastest memories (like registers) are made from DFFs.