Why is out = 1 when all the control bits are set to 1?

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Why is out = 1 when all the control bits are set to 1?

wetFence
According to this table:


When all the control bits are set to 1, the output is 1.

But why?

If I look at the table:
x=0 because zx is set
x=1 because nx is set
y=0 because zy is set
y=1 because ny is set
out=1+1 => out=1 OR 1 => out=1 because f is set
out=!1 => out=0 because no is set

But why does the second line say that out=1 when all 6 control bits are set then? What am I missing?
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Re: Why is out = 1 when all the control bits are set to 1?

cadet1620
Administrator
wetFence wrote
When all the control bits are set to 1, the output is 1.

But why?

If I look at the table:
x=0 because zx is set
x=1 because nx is set
y=0 because zy is set
y=1 because ny is set
out=1+1 => out=1 OR 1 => out=1 because f is set
The ALU is a 16-bit part, so
    (zx == 1) => x =           0000 0000 0000 0000
    (nx == 1) => x = ~x =      1111 1111 1111 1111 (-1)
    (zx == 1) => y =           0000 0000 0000 0000
    (nx == 1) => y = ~y =      1111 1111 1111 1111 (-1)
    (f == 1)  => out = x + y = 1111 1111 1111 1110 (-2)
    (no == 1) => out = ~out =  0000 0000 0000 0001 (1)
You might want to check out this worksheet.

--Mark
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Re: Why is out = 1 when all the control bits are set to 1?

wetFence
I see my mistake now, thanks. 1 + 1 = 10 => 0 but I did 1 + 1 = 1
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Re: Why is out = 1 when all the control bits are set to 1?

sleazy_b
In reply to this post by cadet1620
I'm actually a little confused about this and the spec appears to be ambiguous. At times nx, ny are said to negate x and y, at other times they are said to not them (that is, apply the not operation).

You seem to be implying here that the two's complement negation of 0 is -1, which is  a bit weird. I see that this is the answer the problem is expecting, but I'm not sure why.

Thanks in advance
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Re: Why is out = 1 when all the control bits are set to 1?

cadet1620
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sleazy_b wrote
I'm actually a little confused about this and the spec appears to be ambiguous. At times nx, ny are said to negate x and y, at other times they are said to not them (that is, apply the not operation).
The nx, ny and no control signals cause logical negation—the Boolean not operator.

See this worksheet mentioned above to understand how logical negation (Not) results in arithmetic negation of 2's-complement integers.

(In a quick scan of chapter 2 it looks like the book consistently uses "arithmetic negation" when it talks about signed integer negation and just "negation" when it talks about Boolean negation.)

--Mark
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