[Updated 11/15/2012 to use the new and smaller Nand ALU.]
This is ybakos' fault. A couple weeks ago he asked me about a Nand only implementation of the Hack CPU. Although I hadn't ever considered designing one, the idea kept nibbling away at my mind. Then I started poking at it in the evenings...
So, here it is, 1186 Nand gates later. New and improved now, with only 1160 Nand gates.
This zip file contains a PDF schematic as well as Logisim and HDL implementations.
Notes on the Logisim circuit
Use the "poke" tool (finger) to set "reset" = 1.
Enable the clock (ctrl+K).
Poke "reset" to 0.
The computer should start printing "Hello world".
Poke the Keyboard and type a new message followed by Enter. The new message should start being displayed.
Notes on the HDL implementation
TECS Hardware Simulator does not simulate feedback, so the DFFs built from Nand gates must be replaced with built-in DFF parts. The Nand gates that compose the DFFs are present, but commented out.
The D register output from the DFFs behaves differently than the output from the DRegister built-in part. (They appear to trigger on different clock edges.) The supplied .tst and .cmp files ignore data changes on the wrong clock edge.